Conventional non-volatile memory devices commonly include a floating gate structure that is formed over the channel region of a semiconductor substrate. During fabrication according to a conventional process, a tunneling oxide layer is formed on the channel region and a conductive floating gate layer is formed on the tunneling oxide layer. An inter-gate dielectric layer is formed on the floating gate layer and a conductive control gate layer is formed on the inter-gate dielectric layer. A hard mask pattern, for example comprising silicon nitride, is then applied to a top surface of the resulting structure, and then patterned to define gate patterns. The control gate layer, the inter-gate dielectric layer, the floating gate layer, and the tunneling oxide layer are then etched to form gate patterns, using the hard mask pattern as an etch mask.
In the conventional fabrication process, the resulting gate structure has a relatively high aspect ratio during patterning of the gate structure using the hard mask pattern. A high aspect ratio can lead to problems during the etching process. In addition, mechanical stress between layers is more likely to cause bowing of the resulting gate structures in the case where the structures have a high aspect ratio. Such bowing can, in turn, lead to electrical bridging between adjacent gates, which can cause device failure. Further, in the conventional approach, the control gate comprises a multiple-layered structure that includes an upper layer comprising a silicide material, for example WSix, which has relatively high resistance properties. Since the control gate is also used as a word line in non-volatile memory devices employing this type of gate structure, a word line of relatively high resistance is formed. This can lead to signal delay in the device, resulting in lower operating speed. Also, the silicide layer can be relatively thick, for example on the order of 1000 angstroms, which contributes to the resulting high aspect ratio of the device. In addition, a lower layer of the control gate comprises a polysilicon material, the outer edges of which can suffer from etch damage during the gate patterning process.
To overcome these limitations, an improved floating gate structure has been devised that is characterized by a reduced aspect ratio and improved resistance properties. In this improved structure, the previous multiple-layered control gate including a lower polysilicon layer and an upper silicide layer is replaced by a multiple-layered control gate including a lower polysilicon layer, an intermediate barrier layer, for example comprising WNx, and an upper metal layer, for example comprising W. The intermediate barrier layer and upper metal layer are relatively thin, for example on the order of 100-300 angstroms, so the resulting aspect ratio of the gate structure is reduced, for example, from about 6.4 in the conventional structure to about 3.1 in the improved structure. The reduced aspect ratio leads to improved reliability in the resulting device, since the likelihood of bowing of the structures is reduced. The intermediate barrier layer further improves adhesion between the upper metal layer and lower polysilicon layer, while at the same time, preventing the silicon atoms of the lower polysilicon layer from reacting with the metal atoms of the metal layer.
In the fabrication process of the improved floating gate structure, a post-oxidation process is performed following etch of the gate patterns, in an effort to mitigate etch damage to sidewalls of the lower polysilicon layer of the control gate. However, as a result of the post-oxidation process, the sidewalls of the metal layer also become oxidized, which can lead to an increase in the resistance of the metal layer, and which can cause delamination between the metal layer and the underlying barrier layer. In addition, following the gate patterning process, polymer particles are difficult to remove. A strong wet etch solvent cannot be applied to remove the polymers because the upper metal layer of the control gate is highly susceptible to wet etch, so exposure to strong wet etch solvents should be limited. The presence of polymer particles between the gates can result in electrical bridging between the gates, which can lead to device failure.